A packet-processing device, like a switch microchip, usually needs to buffer the packets into a packet memory (PM) having one or more banks while the device processes them. Specifically, the ingress ports and the associated ingress port logic (write clients) need to receive packets and write packet data to the packet memory while the device processes portions of the packet. Similarly, the egress ports and the associated egress port logic (read clients) need to read the packet data from the packet memory and output the packets from the device when the processing of the packet has completed. The number of read/write clients needed on the device depends on the bandwidth requirements of the device. In high-performance switch chips, this number can be in the hundreds, so an implementation where each client has a dedicated interface to read or write data to/from the PM is unfeasible due to the large number of wires that are needed to be routed from the clients to the PM. Additionally, the read/write clients are usually physically placed in the periphery of the device (e.g. switch die) whereas the PM is in the middle, thereby exacerbating the problem of routing that many wires between the ports and the PM. As a result, this scheme is not physical friendly because it requires lots of wide interfaces to be routed from the periphery of the die to the center of the die, typically using expensive routing resources (top-level metal layers). Also, due to the large distances these interface busses need to travel, several stages of sequential cells (flops) are needed to be inserted to meet the target clock frequency.